VERILOG CODE AND TEST BENCH for 8X1 MUX Using 2X1 MUX

  EXPLANATION:

              A multiplexer or in short mux is a combinational logic circuit used to pass only one of the multiple inputs(i0,i1,i2,i3,i4,i5,i6,i7) at a time with the help of select lines(s0,s1,s2) to generate the output(y).

               A 8x1(Four cross one) mux has Eight inputs and 1 output. The output of a mux will always be one. The general formulae for all types of multiplexers is, For 2ⁿ  inputs, the number of selects line will be n.

               For 8x1 mux when s=000, the input line i0 will be transferred to the output y; when s=001, the input line i1 will be transferred to the output y; when s=010, the input line i2 will be transferred to the output y; when s=011, the input line i3 will be transferred to the output y and so on.

 Fig 1.  Block Diagram of 8X1 MUX

^{RTL VIEW:}

                                                      As shown in the RTL, to form 8X1 mux, Seven 2X1 mux are required. 2X1 Mux's in the first column will have s[0] as the select line, 2X1 Mux's in the Second column will have s[1] as the select line,  2X1 Mux's in the Third and last column will have s[3] as the select line.

Verilog code:

For 8X1 MUX(Top module)

module mux8_1(i,s,y);

input [7:0]i;

input [2:0]s;

output y;

wire w1,w2,w3,w4,w5,w6;

mux2_1 m1(.i0(i[0]),.i1(i[1]),.s(s[0]),.y(w1));

mux2_1 m2(.i0(i[2]),.i1(i[3]),.s(s[0]),.y(w2));

mux2_1 m3(.i0(i[4]),.i1(i[5]),.s(s[0]),.y(w3));

mux2_1 m4(.i0(i[6]),.i1(i[7]),.s(s[0]),.y(w4));

mux2_1 m5(.i0(w1),.i1(w2),.s(s[1]),.y(w5));

mux2_1 m6(.i0(w3),.i1(w4),.s(s[1]),.y(w6));

mux2_1 m7(.i0(w5),.i1(w6),.s(s[2]),.y(y));

endmodule

For 2X1 MUX:

module mux2_1(input i0,i1,s,output y);

assign y=(s==0)? i0:i1;

endmodule

Test Bench:

`timescale 1ns/1ns

module tb;

reg [7:0]i;

reg [2:0]s;

wire y;

mux8_1   DUT(i,s,y);

initial 

begin

i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

#15 i=$random;s=$random;

end

endmodule

WAVEFORM:

Fig 2. Output Waveform of 4X1 MUX

CONCLUSION:

For 8x1 mux when s=000, the input line i0 will be transferred to the output y; when s=001, the input line i1 will be transferred to the output y; when s=010, the input line i2 will be transferred to the output y; when s=011, the input line i3 will be transferred to the output y and so on.

Be free to comment any doubts.


Cheers to you all..