VERILOG CODE AND TEST BENCH for 2X1 MUX Using assign statement

 EXPLANATION:

               A multiplexer or in short mux is a combinational logic circuit used to pass only one of the multiple inputs(i0,i1) at a time with the help of select lines(s) to generate the output(y). A 2x1(Two cross one) mux has two inputs and 1 output. 

              The output of a mux will always be one. The general formulae for all types of multiplexers is, For 2ⁿ  inputs, the number of selects line will be n. 

               For 2x1 mux when s=0, the input line i0 will be transferred to the output y and  when s=1, the input line i1 will be transferred to the output y.  

               

Fig 1. Block Diagram of 2X1 MUX

Verilog code:

module mux2_1(input s,i0,i1,output y);

assign y=((~s)&i0)|(s&i1);

endmodule

Test Bench:

`timescale 1ns/1ns

module tb;

reg s,i0,i1;

wire y;

mux2_1  DUT(s,i0,i1,y);

initial 

begin

s=1'b0;i0=1'b0;i1=1'b0;

#15 s=1'b0;i0=1'b0;i1=1'b1;

#15 s=1'b0;i0=1'b1;i1=1'b0;

#15 s=1'b0;i0=1'b1;i1=1'b1;

#15 s=1'b1;i0=1'b0;i1=1'b0;

#15 s=1'b1;i0=1'b0;i1=1'b1;

#15 s=1'b1;i0=1'b1;i1=1'b0;

#15 s=1'b1;i0=1'b1;i1=1'b1;

end

endmodule

WAVEFORM:

CONCLUSION:

For 2x1 mux when s=0, the input line i0 will be transferred to the output y and  when s=1, the input line i1 will be transferred to the output y.  

Be free to ask any doubt.


Cheers to you all..