VERILOG CODE AND TEST BENCH for 4X1 MUX Using Case statement

    EXPLANATION:

              A multiplexer or in short mux is a combinational logic circuit used to pass only one of the multiple inputs(i0,i1,i2,i3) at a time with the help of select lines(s0,s1) to generate the output(y).

               A 4x1(Four cross one) mux has four inputs and 1 output. The output of a mux will always be one. The general formulae for all types of multiplexers is, For 2ⁿ  inputs, the number of selects line will be n.

               For 4x1 mux when s=00, the input line i0 will be transferred to the output y; when s=01, the input line i1 will be transferred to the output y; when s=10, the input line i2 will be transferred to the output y; when s=11, the input line i3 will be transferred to the output y.

               

                                                        Fig 1.  Block Diagram of 4X1 MUX

Verilog code:

module mux4_1(i0,i1,i2,i3,s,y);

input i0,i1,i2,i3;

input [1:0]s;

output reg y;

always@(*)

begin

case(s)

2'b00: y=i0;

2'b01: y=i1;

2'b10: y=i2;

2'b11: y=i3;

endcase

end

endmodule

Test Bench:

`timescale 1ns/1ns

module tb;

reg i0,i1,i2,i3;

reg [1:0]s;

wire y;

mux4_1   DUT(i0,i1,i2,i3,s,y);

initial 

begin

s=2'b00;i0=1'b0;i1=1'b0;i2=1'b0;i3=1'b0;

#15 s=2'b01;i0=1'b0;i1=1'b0;i2=1'b0;i3=1'b1;

#15 s=2'b01;i0=1'b0;i1=1'b0;i2=1'b1;i3=1'b0;

#15 s=2'b11;i0=1'b0;i1=1'b0;i2=1'b1;i3=1'b1;

#15 s=2'b01;i0=1'b0;i1=1'b1;i2=1'b0;i3=1'b0;

#15 s=2'b10;i0=1'b0;i1=1'b1;i2=1'b0;i3=1'b1;

#15 s=2'b00;i0=1'b0;i1=1'b1;i2=1'b1;i3=1'b0;

#15 s=2'b01;i0=1'b1;i1=1'b0;i2=1'b0;i3=1'b0;

#15 s=2'b11;i0=1'b1;i1=1'b0;i2=1'b0;i3=1'b1;

#15 s=2'b01;i0=1'b1;i1=1'b0;i2=1'b1;i3=1'b0;

#15 s=2'b10;i0=1'b1;i1=1'b0;i2=1'b1;i3=1'b1;

#15 s=2'b01;i0=1'b1;i1=1'b1;i2=1'b0;i3=1'b0;

#15 s=2'b00;i0=1'b1;i1=1'b1;i2=1'b0;i3=1'b1;

#15 s=2'b11;i0=1'b1;i1=1'b1;i2=1'b1;i3=1'b0;

#15 s=2'b01;i0=1'b1;i1=1'b1;i2=1'b1;i3=1'b1;

end

endmodule

WAVEFORM:

Fig 2. Output Waveform of 4X1 MUX

CONCLUSION:

For 4x1 mux when s=00, the input line i0 will be transferred to the output y; when s=01, the input line i1 will be transferred to the output y; when s=10, the input line i2 will be transferred to the output y; when s=11, the input line i3 will be transferred to the output y.

Be free to comment any doubts.


Cheers to you all..